Design of an Error Detection Fault Tolerant Arbiter for a Network on Chip - Naddunoori, Malathi; M. , Devanathan (International Journal of Intelligent Systems and Applications in Engineering, 2024)
Device to Device communications and System-on-Chip (SoC) communications needs thehigh-speed data transfer with low hardware resource utilization. However, the conventional methods have resulted in higher area, high power consumption including time delay .This paper thus proposes the concept of Fault Tolerant Arbiter based Network on Chip (FTA-NoC)architecture with FIFO-Buffer, crossbar switching, route control, and arbiter modules. This work presents encoder and decoder-based route controlling using fault tolerant arbiter, which was introduced for high speed, error-free route calculation with less hardware resources in NOC.Initially, data generated from the different devices is stored into FIFO-Buffer logic, which allocates the data based on IP addresses. Then, route controller module controls the different routers in crossbar switching, which arecontrolled by priority-based scheduling. The data is then sent from the source to the destination using arbitrator in accordance with request levels. The simulation results show how well the FTA-NOC performs in terms of area, latency, and power when compared to the most advanced NoC architectures.