Implementation of 8th Order Delta Sigma Modulation with Reconfigurable Multiple Bandwidth using Truncated Method on FPGA - Arun Raj S. R (International Journal of Intelligent Systems and Applications in Engineering, 2024)
In modern wireless communication technology, an energy and spectrum efficient reconfigurable transmitter design with a high data rate is required; and the conventional systems are wasteful during amplification. For high data rate transmission, LTE-A supports a reconfigurable transmitter design with carrier spacing and continuous carrier aggregation. This study shows how the carrier signal’s wide bandwidth is fragmented into several smaller sub-carriers, thus 5G applications need multiband transmission. This work presents an 8th order reconfigurable multi-band delta sigma modulator (RMB - DSM) that enables the noise transfer function zero to be modified to fall at multiple carrier aggregation frequencies. When using several transmission bands, quantization noise between the bands becomes a major issue. Thus, we implement a multi-band additional noise shaping (ANS) function, which greatly reduces on noise over a range of pass-bands by creating notches around each carrier. Systematically designing a 4th order reconfigurable multi-band delta sigma modulator will increase logic size and energy consumption, and the logic’s arithmetic operations will need a significant amount of logic in VLSI implementation. The 8th order reconfigurable multi-band delta sigma modulator given in the suggested study is an energy quality scalable truncated technology that would lower the quantity of logic size in arithmetic operations. With these truncated methods, the RMB-DSM architecture’s internal and external logic are reduced, and the n x n multiplication yields just n-size output. The proposed approach has been proven by simulation and experiment for aggregating up to four and eight multiband long term evolution (LTE) signals, yielding a total bandwidth of and a sampling frequency of 1 GHz. The Xilinx Zynq 7000 FPGA will be used to implement both existing and proposed designs, and their logic size, latency, and power consumption will be compared.