A Low-delay Configurable Register for FPGA using GDI Technique - T Adithya Nag Venkat (International Journal of Intelligent Systems and Applications in Engineering, 2024)
The fundamental building block of FPGA (Field Programmable Gate Array) is the CLB (Configurable Logic Block). The sequential component of a CLB is a Configurable register. The goal of this paper is to show how to reduce the area of a low delay configurable register without significantly affecting its latency. To achieve this, we employed the GDI (Gate Diffusion Input) approach, which is well known for drastically reducing the transistor count. The GDI logic operates slightly different than a 2x1 mux. The primary issue with this technique is that it produces weak signals (weak 0s and weak 1s), while reducing the number of transistors. In this paper, we cleverly addressed the issue.