FPGA Implementation of Adaptive Hold Logic Vedic Fused Dot Product Floating-Point Multiplier Using Razor Flip -Flop - Erna, G.; Saidulu, V.; Srihari, G.; Rao, K. Babu (International Journal of Intelligent Systems and Applications in Engineering, 2023)
In the recent technology of high-speed digital signal processing system has been increases with the explosive growth in mobile computing and portable multimedia application. In this digital signal processing method of arithmetic operation will have more number of floating point multipliers it will used in FFT and DCT based applications, but it will have more latency and less throughput and also take more area consumptions. Thus, this proposed work introduced to Reduced the latency in floating point multiplication with fused method, therefore here fused method integrated with Vedic multiplier using AHL and Razor flip flop. Here, this proposed work will Designed at 16-bit size in Verilog HDL, and it will Synthesized in Xilinx FPGA S6LX9-2TQG144, and finally compared all the parameters in terms of area, delay and power.